The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Feb. 23, 2018
Applicant:

Netspeed Systems, San Jose, CA (US);

Inventors:

Anup Gangwar, Bangalore, IN;

Vishnu Mohan Pusuluri, Bangalore, IN;

Poonacha Kongetira, Saratoga, CA (US);

Sailesh Kumar, San Jose, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 1/26 (2006.01); G06F 1/324 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); Y02D 10/126 (2018.01); Y02D 10/171 (2018.01); Y02D 10/172 (2018.01); Y02D 50/20 (2018.01);
Abstract

Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.


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