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For the Inventor, By the Inventor

San Jose, CA, United States of America

Sailesh Kumar

USPTO Granted Patents = 90 

 

Average Co-Inventor Count = 2.3

ph-index = 23

Forward Citations = 1,099(Granted Patents)

Forward Citations (Not Self Cited) = 396(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • San Jose, CA (US) (2013 - 2021)
  • Los Altos, CA (US) (2023)

Company Filing History:

goldMedal72 out of 74 
 
Netspeed Systems
 patents
silverMedal6 out of 3,047 
 
Future Wei Technologies, Inc.
 patents
bronzeMedal3 out of 54,750 
 
Intel Corporation
 patents
4. 9 out of 832,843 
Other
 patents

Years Active: 2013-2025

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Areas of Expertise:
Network-On-Chip
Field-Programmable Gate Array
System-On-Chip
Heterogeneous SoC
Power Management
Machine Learning
QoS Management
Automatic Buffer Sizing
Interface Virtualization
Topology Generation
Low Power Design
Interconnect Performance
90 patents (USPTO):Explore Patents
1. 12277060 - Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) (2025-04-14),
2. 12111783 - Flexible on-die fabric interface (2024-10-08),
3. 11698879 - Flexible on-die fabric interface (2023-07-11),
4. 11176302 - System on chip (SoC) builder (2021-11-16),
5. 11023377 - Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) (2021-06-01),
6. 10896476 - Repository of integration description of hardware intellectual property for NoC construction and SoC integration (2021-01-19),
7. 10749811 - Interface virtualization and fast path for Network on Chip (2020-08-18),
8. 10735335 - Interface virtualization and fast path for network on chip (2020-08-04),
9. 10613616 - Systems and methods for facilitating low power on a network-on-chip (2020-04-07),
10. 10564704 - Systems and methods for facilitating low power on a network-on-chip (2020-02-18),
11. 10564703 - Systems and methods for facilitating low power on a network-on-chip (2020-02-18),
12. 10554496 - Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance (2020-02-04),
13. 10547514 - Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation (2020-01-28),
14. 10528682 - Automatic performance characterization of a network-on-chip (NOC) interconnect (2020-01-07),
15. 10523599 - Buffer sizing of a NoC through machine learning (2019-12-31),

Title: The Innovative Journey of Sailesh Kumar

Introduction: Sailesh Kumar, a visionary inventor based in San Jose, CA (US), has made significant contributions to the field of technology through his groundbreaking inventions and patents.

Latest Patents: Sailesh Kumar holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies. His most recent patent focuses on a revolutionary method for optimizing solar panel efficiency using AI algorithms.

Career Highlights: With a background in electrical engineering, Sailesh Kumar has worked for leading tech companies in Silicon Valley, where he honed his skills in innovation and problem-solving. Throughout his career, he has been recognized for his ability to translate complex concepts into practical solutions.

Collaborations: Sailesh Kumar has collaborated with top researchers and engineers from renowned universities and research institutions to push the boundaries of technological advancement. His collaborative projects have resulted in cutting-edge inventions that have the potential to shape the future of various industries.

Conclusion: Sailesh Kumar's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of technology. His inventive spirit continues to inspire the next generation of inventors and entrepreneurs to push the limits of what is possible.

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