The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Mar. 16, 2018
Applicant:

Netspeed Systems, Inc., San Jose, CA (US);

Inventors:

Nishant Rao, San Jose, CA (US);

Sailesh Kumar, San Jose, CA (US);

Pier Giorgio Raponi, San Jose, CA (US);

Assignee:

NetSpeed Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/24 (2006.01); H04L 12/933 (2013.01);
U.S. Cl.
CPC ...
H04L 41/12 (2013.01); H04L 49/101 (2013.01); H04L 49/109 (2013.01);
Abstract

A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.


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