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Sunnyvale, CA, United States of America

Monterey Design Systems, Inc.

USPTO Granted Patents = 14

Forward Citations = 742

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38 inventors (with patents filed for the assignee):

Douglas B Boyle (8 out of 33 patents)

Lawrence Thomas Pileggi (8 out of 33 patents)

Sharad Malik (5 out of 17 patents)

4. Salil Ravindra Raje (5 out of 19 patents)

5. Abhijeet Chakraborty (5 out of 8 patents)

6. Majid Sarrafzadeh (4 out of 32 patents)

7. Gary K Yeap (4 out of 13 patents)

8. Feroze P Taraporevala (3 out of 11 patents)

9. Ara Markosian (3 out of 4 patents)

10. Tong Gao (3 out of 3 patents)

11. James S Koford (3 out of 80 patents)

12. Lilly Shieh (2 out of 3 patents)

13. Dennis Yamamoto (2 out of 3 patents)

14. Dinesh D Gaitonde (2 out of 2 patents)

15. Padmini Gopalakrishnan (2 out of 2 patents)

14 patents: Sort by Forward Citations

1. 6775808 - Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits (2004-08-10),

2. 6651232 - Method and system for progressive clock tree or mesh construction concurrently with physical design (2003-11-18),

3. 6567967 - Method for designing large standard-cell base integrated circuits (2003-05-20),

4. 6557145 - Method for design optimization using logical and physical information (2003-04-29),

5. 6523161 - Method to optimize net lists using simultaneous placement and logic optimization (2003-02-18),

6. 6449761 - Method and apparatus for providing multiple electronic design solutions (2002-09-10),

7. 6449756 - Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design (2002-09-10),

8. 6446239 - Method and apparatus for optimizing electronic design (2002-09-03),

9. 6442743 - Placement method for integrated circuit design using topo-clustering (2002-08-27),

10. 6385760 - System and method for concurrent placement of gates and associated wiring (2002-05-07),

11. 6367051 - System and method for concurrent buffer insertion and placement of logic gates (2002-04-02),

12. 6286128 - Method for design optimization using logical and physical information (2001-09-04),

13. 6192508 - Method for logic optimization for improving timing and congestion during placement in integrated circuit design (2001-02-20),

14. 6099580 - Method for providing performance-driven logic optimization in an (2000-08-08),

Monterey Design Systems, Inc. is a leading provider of electronic design automation (EDA) software solutions for the semiconductor industry. Their cutting-edge tools help semiconductor companies design and manufacture innovative chips for a wide range of applications. With a focus on efficiency and quality, Monterey Design Systems, Inc. continues to push the boundaries of technology to drive the industry forward.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 30 2025

14 Patents

#202 in Sunnyvale, CA

#5,156 in California

#21,638 in US

#40,936 in the World

Sunnyvale, CA, United States of America

Monterey Design Systems, Inc.

Forward Citations = 742

38 inventors:

Douglas B Boyle (8 out of 33 patents)

Lawrence Thomas Pileggi (8 out of 33 patents)

Sharad Malik (5 out of 17 patents)

4. Salil Ravindra Raje (5 out of 19 patents)

5. Abhijeet Chakraborty (5 out of 8 patents)

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