The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2002
Filed:
Jun. 12, 1998
Applicant:
Inventors:
Lawrence Pileggi, Pittsburgh, PA (US);
Sharad Malik, Princeton, NJ (US);
Emre Tuncer, Palo Alto, CA (US);
Abhijeet Chakraborty, Sunnyvale, CA (US);
Satyamurthy Pullela, Cupertino, CA (US);
Altan Odabasioglu, Sunnyvale, CA (US);
Douglas B. Boyle, Palo Alto, CA (US);
Assignee:
Monterey Design Systems, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.