The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2002
Filed:
Jun. 12, 1998
Applicant:
Inventors:
Lawrence Pileggi, Pittsburgh, PA (US);
Majid Sarrafzadeh, Wilmette, IL (US);
Gary K. Yeap, San Jose, CA (US);
Feroze Peshotan Taraporevala, San Jose, CA (US);
Tong Gao, Fremont, CA (US);
Douglas B. Boyle, Palo Alto, CA (US);
Assignee:
Monterey Design Systems, Inc., Sunnyvale, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.
Pileggi, Lawrence. (2002). System and method for concurrent placement of gates and associated wiring (U.S. Patent No. 6385760). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6385760
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile