The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2003
Filed:
Oct. 03, 2000
Applicant:
Inventors:
Padmini Gopalakrishnan, Sunnyvale, CA (US);
Salil Raje, San Jose, CA (US);
Assignee:
Monterey Design Systems, Inc., Sunnyvale, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; H01L 2/182 ;
U.S. Cl.
CPC ...
G06F 1/750 ; H01L 2/182 ;
Abstract
Method to optimize net lists used in the design and fabrication of integrated circuits by using simultaneous placement optimization, logic function optimization and net buffering algorithms. Method simultaneously obtains a placement of logic functions, mapping of logic functions on to library elements and buffering of nets connecting the logic functions.
Gopalakrishnan, Padmini. (2003). Method to optimize net lists using simultaneous placement and logic optimization (U.S. Patent No. 6523161). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6523161
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile