The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2001
Filed:
Jun. 12, 1998
Lawrence Pileggi, Pittsburgh, PA (US);
Majid Sarrafzadeh, Wilmette, IL (US);
Sharad Malik, Princeton, NJ (US);
Abhijeet Chakraborty, Sunnyvale, CA (US);
Archie Li, Mountain View, CA (US);
Robert Eugene Shortt, Sunnyvale, CA (US);
Christopher Dunn, Sunnyvale, CA (US);
David Gluss, Woodside, CA (US);
Dennis Yamamoto, Los Altos, CA (US);
Dinesh Gaitonde, Sunnyvale, CA (US);
Douglas B. Boyle, Palo Alto, CA (US);
Emre Tuncer, Palo Alto, CA (US);
Eric McCaughrin, Oakland, CA (US);
Feroze Peshotan Taraporevala, San Jose, CA (US);
Gary K. Yeap, San Jose, CA (US);
James S. Koford, San Jose, CA (US);
Joseph T. Rahmeh, Austin, TX (US);
Lilly Shieh, Union City, CA (US);
Salil R. Raje, Santa Clara, CA (US);
Sam Jung Kim, San Jose, CA (US);
Satamurthy Pullela, Cupertino, CA (US);
Yau-Tsun Steven Li, Causeway Bay, HK;
Tong Gao, Fremont, CA (US);
Monterey Design Systems, Inc., Sunnyvale, CA (US);
Abstract
A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.