This inventor holds 1 USPTO granted patent. Top assignee: Monterey Design Systems, Inc.. Active years: 2001.
Company Filing History:
Years Active: 2001
Title: The Innovative Mind of Satamurthy Pullela
Introduction
Satamurthy Pullela is a notable inventor based in Cupertino, CA (US). He has made significant contributions to the field of integrated circuit design through his innovative methods. His work focuses on optimizing design processes, which is crucial in the ever-evolving technology landscape.
Latest Patents
Pullela holds a patent titled "Method for design optimization using logical and physical information." This patent describes a method that includes receiving a behavioral description of an integrated circuit or a portion of it. The process involves optimizing the placement of circuit elements according to a first cost function and optimizing the logic of these elements according to a second cost function. Notably, these optimizations are performed concurrently, enhancing efficiency. Additionally, the method includes optimizing routing in accordance with a third cost function, further streamlining the design process.
Career Highlights
Satamurthy Pullela is associated with Monterey Design Systems, Inc., where he applies his expertise in integrated circuit design. His innovative approach has positioned him as a valuable asset in the field. With a patent portfolio that includes 1 patent, he continues to contribute to advancements in technology.
Collaborations
Pullela has collaborated with talented individuals such as Eric McCaughrin and Lilly Shieh. These partnerships have fostered a creative environment that encourages innovation and the development of cutting-edge solutions.
Conclusion
Satamurthy Pullela's contributions to integrated circuit design through his patented methods exemplify the spirit of innovation. His work not only enhances design optimization but also sets a foundation for future advancements in the field.