The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2002
Filed:
Jun. 12, 1998
Majid Sarrafzadeh, Wilamette, IL (US);
Lawrence Pileggi, Pittsburgh, PA (US);
Sharad Malik, Princeton, NJ (US);
Feroze Peshotan Taraporevala, San Jose, CA (US);
Abhijeet Chakraborty, Sunnyvale, CA (US);
Gary K. Yeap, San Jose, CA (US);
Salil R. Raje, Santa Clara, CA (US);
Lilly Shieh, Union City, CA (US);
Douglas B. Boyle, Palo Alto, CA (US);
Dennis Yamamoto, Los Altos, CA (US);
Monterey Design Systems, Sunnyvale, CA (US);
Abstract
The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.