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For the Inventor, By the Inventor

San Jose, CA, United States of America

Microsemi Soc Corporation

Calculating rank
USPTO Granted Patents = 71

% Expired Patents = 4.2

Trademarks = 6

Forward Citations = 176

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48 inventors (with patents filed for the assignee):

goldMedal John L McCollum (36 out of 159 patents)

silverMedal Jonathan W Greene (21 out of 61 patents)

bronzeMedal Fethi Dhaoui (13 out of 42 patents)

4.  Volker Hecht (9 out of 29 patents)

5.  Frank W Hawley (8 out of 42 patents)

6.  G Richard Newell (5 out of 5 patents)

7.  Fengliang Xue (4 out of 8 patents)

8.  Victor Nguyen (3 out of 7 patents)

9.  Ming-Hoe Kiu (3 out of 3 patents)

10.  Prakash Reddy (3 out of 3 patents)

11.  Wenyi Feng (3 out of 10 patents)

12.  Joel D Landry (3 out of 11 patents)

13.  Jongsok Choi (2 out of 5 patents)

14.  William C Plants (2 out of 111 patents)

15.  Pavan Singaraju (2 out of 2 patents)


Core Competencies:
ReRAM Cells
FPGA Design
Memory Arrays
Analog Neural Networks
Hybrid Devices
Non-Volatile Memory
Integrated Circuits
Low-Power Configurations
Digital Signal Processing
Security Methods
Fast Data Erase
Fault Detection

71 patents:

1. 12763774 - Apparatus including a CMOS pass gate circuit and a bootstrap circuit (2026-10-13),
2. 12755777 - CMOS memory cell for high voltage applications (2026-10-06),
3. 12694181 - High-level-synthesis for RISC-V system-on-chip generation for field programmable gate arrays (2026-07-28),
4. 12664323 - Tamper detector based on power network electrical characteristic (2026-06-23),
5. 12591723 - Generating RTL for a circuit using DSP blocks (2026-03-31),
6. 12154622 - ReRAM memory array that includes ReRAM memory cells having a ReRAM device and two series-connected select transistors that can be selected for erasing (2024-11-26),
7. 11544349 - Method for combining analog neural net with FPGA routing in a monolithic integrated circuit (2023-01-03),
8. 11114348 - Hybrid high-voltage low-voltage FinFET device (2021-09-07),
9. 11031078 - SEU stabilized memory cells (2021-06-08),
10. 11023559 - Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit (2021-06-01),
11. 10971216 - SRAM configuration cell for low-power field programmable gate arrays (2021-04-06),
12. 10936286 - FPGA logic cell with improved support for counters (2021-03-02),
13. 10855286 - Front to back resistive random-access memory cells (2020-12-01),
14. 10714180 - Hybrid configuration memory cell (2020-07-14),
15. 10650890 - Circuitry and methods for programming resistive random access memory devices (2020-05-12),
Company Overview
Microsemi Soc Corporation, based in San Jose, California, specializes in advanced semiconductor solutions, particularly in ReRAM technology. The company focuses on developing innovative ReRAM cells and integrated circuits that support low-power configurations and non-volatile memory applications. Its expertise extends to FPGA design, memory arrays, and analog neural networks, positioning Microsemi as a key player in the fields of hybrid devices and memory technology, catering to a diverse range of industries and applications.
Profile summary synthesized from public USPTO records and patent filings.

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USPTO Data Jan 1 1976 - Oct 20 2026

Microsemi Soc Corporation USPTO Patent Assignee Logo
71 Patents

#146 in San Jose, CA

#1,214 in California

#5,169 in US

#10,513 in the World

San Jose, CA (US)
San Jose, CA, United States of America

Microsemi Soc Corporation

Forward Citations = 176

48 inventors:

goldMedal John L McCollum (36 out of 159 patents)

silverMedal Jonathan W Greene (21 out of 61 patents)

bronzeMedal Fethi Dhaoui (13 out of 42 patents)

4.  Volker Hecht (9 out of 29 patents)

5.  Frank W Hawley (8 out of 42 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Microsemi Soc Corporation. Retrieved from https://idiyas.com/company/microsemi-soc

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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