The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Nov. 01, 2018
Applicant:

Microsemi Soc Corp., San Jose, CA (US);

Inventors:

Jonathan W. Greene, Palo Alto, CA (US);

John McCollum, Orem, UT (US);

Assignee:

Microsemi SoC Corp., Chandler, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); H03K 19/1776 (2020.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); H03K 19/1776 (2013.01); G11C 11/419 (2013.01);
Abstract

A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.


Find Patent Forward Citations

Greene, Jonathan. (2021). Sram configuration cell for low-power field programmable gate arrays (U.S. Patent No. 10971216). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10971216

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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