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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11114348 B1

PDFFull Text
Date of Patent:
Sep. 07, 2021

Filed:

Nov. 01, 2018

Hybrid high-voltage low-voltage finfet device

Applicant:

Microsemi Soc Corp., San Jose, CA (US);

Inventors:

John McCollum, Orem, UT (US);

Fethi Dhaoui, Mountain House, CA (US);

Pavan Singaraju, San Jose, CA (US);

Assignee:

Microsemi SoC Corp., San Jose, CA (US);

Attorneys:

Glass & Associates

Kenneth D'Alessandro

Kenneth Glass

Primary Examiner:

Marcos D Pizarro

Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 27/11 (2006.01); H01L 21/26 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/845 (2013.01); H01L 21/02164 (2013.01); H01L 21/26 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 27/0886 (2013.01); H01L 27/1104 (2013.01); H01L 27/1108 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.

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