The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jan. 29, 2019
Applicant:

Microsemi Soc Corp., San Jose, CA (US);

Inventors:

Jonathan Greene, Palo Alto, CA (US);

Frank Hawley, Campbell, CA (US);

John McCollum, Orem, UT (US);

Assignee:

Microsemi SoC Corp., Chandler, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/1776 (2020.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H03K 19/17724 (2020.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/085 (2013.01); H01L 45/122 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/1266 (2013.01); H01L 45/141 (2013.01); H01L 45/142 (2013.01); H01L 45/149 (2013.01); H01L 45/16 (2013.01); H01L 45/1616 (2013.01); H01L 45/1625 (2013.01); H01L 45/1675 (2013.01); H03K 19/17724 (2013.01); H01L 45/08 (2013.01); Y10S 438/90 (2013.01);
Abstract

A resistive random-access memory device formed on a semiconductor substrate includes a first interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via has a top surface extending above a top surface of the chemical-mechanical-polishing stop layer. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer extend beyond outer edges of the first via. A second interlayer dielectric layer including a second via is formed over the dielectric layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.


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