For the Inventor, By the Inventor

Enter assignee name

Santa Clara, CA, United States of America

Lovoltech, Incorporated

USPTO Granted Patents = 36

% Expired Patents = 50.0

Forward Citations = 571

Loading Chart...

Loading Chart...

9 inventors (with patents filed for the assignee):

Ho-Yuan Yu (27 out of 50 patents)

Valentino Liva (4 out of 15 patents)

Pete Pegler (4 out of 4 patents)

4. Chong Ming Lin (3 out of 39 patents)

5. Ho Yuan Yu (3 out of 5 patents)

6. William Planey (2 out of 2 patents)

7. Eric Earl Johnson (1 out of 8 patents)

8. Daniel Chang (1 out of 4 patents)

9. Bill Planey (1 out of 1 patent)

Core Competencies:

Flip-Chip Packaging

JFET

MESFET

Electrostatic Discharge

High Voltage

Low Voltage

Circuit Design

Power Supply

Rectifier Circuits

Enhancement Mode

Buck Converter

Guard Ring

36 patents: Sort by Forward Citations

1. 7122885 - Flip-chip packaging (2006-10-17),

2. 7098634 - Buck-boost circuit with normally off JFET (2006-08-29),

3. 7075132 - Programmable junction field effect transistor and method for programming the same (2006-07-11),

4. 7045397 - JFET and MESFET structures for low voltage high current and high frequency applications (2006-05-16),

5. 7038260 - Dual gate structure for a FET and method for fabricating same (2006-05-02),

6. 7009229 - Electrostatic discharge protection device for integrated circuits (2006-03-07),

7. 7009228 - Guard ring structure and method for fabricating same (2006-03-07),

8. 6995052 - Method and structure for double dose gate in a JFET (2006-02-07),

9. 6975157 - Starter device for normally off JFETs (2005-12-13),

10. 6921932 - JFET and MESFET structures for low voltage, high current and high frequency applications (2005-07-26),

11. 6900506 - Method and structure for a high voltage junction field effect transistor (2005-05-31),

12. 6887768 - Method and structure for composite trench fill (2005-05-03),

13. 6812079 - Method for a junction field effect transistor with reduced gate capacitance (2004-11-02),

14. 6777722 - Method and structure for double dose gate in a JFET (2004-08-17),

15. 6774417 - Electrostatic discharge protection device for integrated circuits (2004-08-10),

Lovoltech, Incorporated is a technology company based in Santa Clara, California, specializing in advanced engineering solutions and innovative product development. The organization focuses on creating cutting-edge technologies in the fields of electronics and software, with applications spanning various industries. Lovoltech is dedicated to enhancing performance and efficiency through research and development, positioning itself as a key player in the evolving landscape of technology and engineering.

Profile summary based on public USPTO records.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

Lovoltech, Incorporated

36 Patents

#98 in Santa Clara, CA

#2,245 in California

#9,502 in US

#18,716 in the World

Santa Clara, CA, United States of America

Lovoltech, Incorporated

Forward Citations = 571

9 inventors:

Ho-Yuan Yu (27 out of 50 patents)

Valentino Liva (4 out of 15 patents)

Pete Pegler (4 out of 4 patents)

4. Chong Ming Lin (3 out of 39 patents)

5. Ho Yuan Yu (3 out of 5 patents)

Please report any incorrect information to [email protected]

Loading…