The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2004

Filed:

Oct. 01, 2003
Applicant:
Inventor:

Pete L. Pegler, Mesa, AZ (US);

Assignee:

Lovoltech, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1337 ;
U.S. Cl.
CPC ...
H01L 2/1337 ;
Abstract

An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described including an appropriately doped substrate forming a drain region, an epitaxial layer formed on top of the substrate, a control structure including a gate region implanted into the epitaxial layer, a source region sharing a p-n junction with the gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either n or p dopants directly below the gate region of either the n-channel or p-channel JFET for widening a depletion region surrounding the gate region. The enlarged depletion region reduces the gate capacitance of the JFET between the gate and drain regions.


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