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San Francisco, CA, United States of America

Kepler Computing Inc.

USPTO Granted Patents = 302

Forward Citations = 1,076

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51 inventors (with patents filed for the assignee):

Sasikanth Manipatruni (298 out of 434 patents)

Rajeev Kumar Dokania (266 out of 268 patents)

Amrita Mathuriya (265 out of 288 patents)

4. Tanay Gosavi (105 out of 169 patents)

5. Noriyuki Sato (101 out of 139 patents)

6. Rafael Rios (83 out of 163 patents)

7. Ikenna Odinaka (79 out of 80 patents)

8. Niloy Mukherjee (63 out of 221 patents)

9. Ramamoorthy Ramesh (62 out of 93 patents)

10. Debo Olaosebikan (62 out of 62 patents)

11. Gaurav Thareja (47 out of 60 patents)

12. Somilkumar J Rathi (42 out of 54 patents)

13. Robert Menezes (30 out of 30 patents)

14. Mauricio Manfrini (29 out of 29 patents)

15. Pratyush Pandey (24 out of 25 patents)

Core Competencies:

Non-Volatile Memory

Capacitor Fabrication

Low Power Multiplier

Asynchronous Full-Adder

Ferroelectric Memory

Wafer Bonding

Stacked Capacitors

Majority Gate

Memory Devices

Doped Polar Layers

3D Stacked Memory

Threshold Gate

302 patents: Sort by Forward Citations

1. 12740066 - Split memory array to reduce bit-line capacitance (2026-09-15),

2. 12727165 - Etch stop layer based integration process for embedded memory (2026-09-01),

3. 12720757 - Method of fabricating a memory device by wafer bonding (2026-08-25),

4. 12718860 - Non-linear polar material based multi-capacitor bit-cell with shared gain element and access transistor (2026-08-25),

5. 12717479 - Method of forming ferroelectric chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer (2026-08-25),

6. 12712005 - MULTI-LEVEL BIT-CELL WITH NON-LINEAR POLAR MATERIAL (2026-08-18),

7. 12676173 - Non-linear polar material based multi-capacitor bit-cell with multi-way sharing of gain element with series transistor (2026-07-07),

8. 12671420 - Method of forming a majority gate based low power ferroelectric based adder with reset mechanism (2026-06-30),

9. 12670942 - Plate-line assist memory (2026-06-30),

10. 12648147 - Method of integrating a memory device with a transistor by hybrid bonding (2026-06-02),

11. 12646549 - Non-linear polar material based multi-capacitor bit-cell with shared gain element with series transistor (2026-06-02),

12. 12640199 - Amplitude modulation for writing to a multi-level bit-cell (2026-05-26),

13. 12640187 - Apparatus to reduce polarization targets or improve memory density for non-linear polar material based memory (2026-05-26),

14. 12635145 - Fabricating non-linear polar material based capacitors for memory and logic (2026-05-19),

15. 12628350 - Manganese or scandium doped ferroelectric device and bit-cell (2026-05-12),

Company Overview

Kepler Computing Inc., based in San Francisco, CA, specializes in advanced non-volatile memory technologies. The company focuses on innovative solutions such as ferroelectric memory and capacitor fabrication, aiming to enhance data storage efficiency and performance. Their research encompasses a range of core technology topics, including low power multipliers, asynchronous full-adders, wafer bonding, stacked capacitors, and majority gates. Kepler Computing is dedicated to pushing the boundaries of memory technology to meet the evolving demands of the digital landscape.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

302 Patents

#24 in San Francisco, CA

#304 in California

#1,451 in US

#2,959 in the World

San Francisco, CA, United States of America

Kepler Computing Inc.

Forward Citations = 1,076

51 inventors:

Sasikanth Manipatruni (298 out of 434 patents)

Rajeev Kumar Dokania (266 out of 268 patents)

Amrita Mathuriya (265 out of 288 patents)

4. Tanay Gosavi (105 out of 169 patents)

5. Noriyuki Sato (101 out of 139 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Kepler Computing Inc.. Retrieved from https://idiyas.com/company/kepler-computing

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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