Split memory array to reduce bit-line capacitance

Abstract

A memory array is split into two or more subarrays with bit-line multiplexers or selection circuitries between the subarrays. Bit-line routes are split along the subarrays via the selection circuitries. The selection circuitries decouple the bit-lines into separate bit-line routes which allow the capacitance on the bit-lines to reduce as parasitic capacitance from the bit-line routes is reduced and bit-line is not driving all the access transistors in a row of the memory array. By using one of the two split bit-lines as the main bit-line, the main bit-line has lower capacitance resulting in faster sensing and better sensing margin since the voltage for sensing on the bit-lines is developed faster, as also larger signal is developed due to lower parasitic capacitance. Further, the access transistor of the selected row can be switched faster which results in higher memory performance. Polarization density requirements also reduce by lowering the parasitic capacitance.