Enter assignee name

Forward Citations = 23

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8 inventors (with patents filed for the assignee):

Kai-Hui Chang (10 out of 11 patents)

Christopher S Browy (5 out of 5 patents)

Hong-zu Chou (3 out of 3 patents)

4. Chi-Lai Huang (3 out of 3 patents)

5. Yen-Ting Liu (3 out of 7 patents)

6. Yueh-Shiuan Tsai (1 out of 1 patent)

7. Andrew Stein (1 out of 1 patent)

8. Chilai Huang (1 out of 1 patent)

10 patents: Sort by Forward Citations

1. 11321507 - System and method for accurate X handling using logic and symbolic cosimulation (2022-05-03),

2. 11263376 - System and method for fixing unknowns when simulating nested clock gaters (2022-03-01),

3. 10852354 - System and method for accelerating real X detection in gate-level logic simulation (2020-12-01),

4. 10794954 - System and method for accelerating timing-accurate gate-level logic simulation (2020-10-06),

5. 10740521 - System and method for localized logic simulation replay using emulated values (2020-08-11),

6. 10726180 - Systems and methods for fixing X-pessimism from uninitialized latches in gate-level simulation (2020-07-28),

7. 10666255 - System and method for compacting X-pessimism fixes for gate-level logic simulation (2020-05-26),

8. 9058452 - Systems and methods for tracing and fixing unknowns in gate-level simulation (2015-06-16),

9. 8938705 - Systems and methods for partial retention synthesis (2015-01-20),

10. 8402405 - System and method for correcting gate-level simulation accuracy when unknowns exist (2013-03-19),

Avery Design Systems, Inc. is a leading provider of verification IP solutions for system-on-chip (SoC) semiconductor design. With a focus on high-performance, easy-to-use verification IP, Avery Design Systems helps customers accelerate their innovation and bring products to market faster. Their comprehensive portfolio of verification IP products includes memory models, protocol monitors, and compliance tests for a wide range of industry standards.

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