The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2022
Filed:
Jun. 23, 2020
Applicant:
Avery Design Systems, Inc., Tewksbury, MA (US);
Inventor:
Kai-Hui Chang, Andover, MA (US);
Assignee:
Avery Design Systems, Inc., Tewksbury, MA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 119/16 (2020.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); H03K 3/012 (2013.01); H03K 3/037 (2013.01); G06F 2119/16 (2020.01); H03K 19/20 (2013.01);
Abstract
A computer executable tool fixes gate-level logic simulation when unknowns (Xs) exist in nested clock gater chains to improve simulation accuracy. Due to X-pessimism in logic simulation, false Xs are generated when simulating nested clock gaters, producing incorrect simulation results. The tool analyzes the fan-in cones along a nested clock gater chain to find such false Xs. Furthermore, it generates auxiliary code to be used with logic simulation to eliminate such false Xs. Gate-level simulation can then be repaired to produce correct results for nested clock gaters.