The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2013
Filed:
May. 22, 2012
Kai-hui Chang, North Andover, MA (US);
Yen-ting Liu, Kaohsiung, TW;
Christopher S. Browy, Boston, MA (US);
Chilai Huang, Andover, MA (US);
Kai-Hui Chang, North Andover, MA (US);
Yen-Ting Liu, Kaohsiung, TW;
Christopher S. Browy, Boston, MA (US);
Chilai Huang, Andover, MA (US);
Avery Design Systems, Inc., Andover, MA (US);
Abstract
This invention provides a system and method for correcting gate-level simulation commences by identifying unknown values (Xs) that are falsely generated during the simulation of a given trace for a design netlist. Then, a sub-circuit of the design netlist is determined for each false X that has inputs of real Xs and an output of a false X. Finally, simulation correction code is generated based on the sub-circuit to eliminate false Xs in simulation of the design netlist. The original design netlist can then be resimulated with the simulation repair code to eliminate false Xs. This allows gate-level simulation to produce correct results.