The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Aug. 30, 2019
Applicant:
Avery Design Systems, Inc., Tewksbury, MA (US);
Inventors:
Assignee:
Avery Design Systems, Inc., Tewksbury, MA (US);
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/30 (2006.01); G06F 30/30 (2020.01); G01R 31/3183 (2006.01); G01R 31/317 (2006.01); G06F 30/33 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G01R 31/318357 (2013.01); G01R 31/31704 (2013.01); G01R 31/318364 (2013.01); G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/398 (2020.01);
Abstract
A computer executable tool analyzes a gate-level netlist and uses an analysis result for accelerating a timing-accurate gate-level logic simulation via a parallel processing. The analysis identifies the following elements in the gate-level netlist: (1) netlist wires at partition boundaries for a value propagation; (2) netlist wires whose activities should be suppressed for a better performance; and (3) upstream FFs for partition boundaries to reduce a synchronization overhead. This information is then used to improve a parallel simulation performance.