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Campbell, CA, United States of America

Arteris, Inc.

USPTO Granted Patents = 96

EPO Patents = 4

Trademarks = 10

Forward Citations = 193

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56 inventors (with patents filed for the assignee):

Benoit De Lescure (34 out of 34 patents)

Moez Cherif (17 out of 17 patents)

John D Coddington (12 out of 26 patents)

4. Parimal Gaikwad (9 out of 12 patents)

5. Craig Stephen Forrest (8 out of 19 patents)

6. Philippe Boucard (8 out of 29 patents)

7. David Alan Kruckemyer (8 out of 13 patents)

8. Syed Ijlal Ali Shah (7 out of 7 patents)

9. Xavier Van Ruymbeke (7 out of 9 patents)

10. Alexis Boutiller (6 out of 6 patents)

11. Monica Tang (6 out of 6 patents)

12. Khaled Labib (5 out of 5 patents)

13. Jonah Probell (5 out of 19 patents)

14. Mohammed Khaleeluddin (5 out of 5 patents)

15. Jean Philippe Loison (4 out of 4 patents)

Core Competencies:

Network-On-Chip

Topology Synthesis

Transaction Aggregation

Deadlock Detection

Performance Prediction

Cache Coherent Interconnect

Broadcast Switch System

Load Balancing

Virtual Channels

Synthesis of Connectivity

Incremental Topology Modification

Quality Metrics

96 patents: Sort by Forward Citations

1. 12524590 - Synthesis of a network-on-chip (NoC) for insertion of pipeline stages (2026-01-13),

2. 12517829 - Processing writes to multiple targets in a directory-based cache coherent electronic system (2026-01-06),

3. 12511466 - System and method for generation of a report and debug of address transformations in electronic systems described with IP-XACT standard (2025-12-30),

4. 12450036 - System and method for scripting generators (2025-10-21),

5. 12438829 - System and method for deadlock detection in network-on-chip (NoC) having external dependencies (2025-10-07),

6. 12411801 - System and method for transaction broadcast in a network on chip (2025-09-09),

7. 12380055 - System and method for performing transaction aggregation in a network-on-chip (NoC) (2025-08-05),

8. 12348382 - Incremental topology modification of a network-on-chip (2025-07-01),

9. 12340156 - System and method for using interface protection parameters (2025-06-24),

10. 12335134 - Network-on-chip (NoC) with a broadcast switch system (2025-06-17),

11. 12289384 - System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC) (2025-04-29),

12. 12237980 - Topology synthesis of a network-on-chip (NoC) (2025-02-25),

13. 12210810 - System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design (2025-01-28),

14. 12204833 - System and method to generate a network-on-chip (NoC) description using incremental topology synthesis (2025-01-21),

15. 12184499 - System and method for editing a network-on-chip (NOC) (2024-12-31),

Arteris, Inc. is a global leader in interconnect IP and AI-centric SoC designs. The company provides SoC fabric technology and interconnect IP solutions to the world's leading semiconductor and automotive companies. Arteris offers innovative and patented technologies for efficient, high-performance, and low-power on-chip communications. With a focus on artificial intelligence and advanced driving assistance systems (ADAS), Arteris enables the smart and connected future.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Jan 20 2026

96 Patents

#4 in Campbell, CA

#900 in California

#3,793 in US

#7,859 in the World

Campbell, CA, United States of America

Arteris, Inc.

Forward Citations = 193

56 inventors:

Benoit De Lescure (34 out of 34 patents)

Moez Cherif (17 out of 17 patents)

John D Coddington (12 out of 26 patents)

4. Parimal Gaikwad (9 out of 12 patents)

5. Craig Stephen Forrest (8 out of 19 patents)

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