For the Inventor, By the Inventor

Enter assignee name

Campbell, CA, United States of America

Arteris, Inc.

USPTO Granted Patents = 103

% Expired Patents = 3.9

EPO Patents = 8

Trademarks = 9

Forward Citations = 207

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62 inventors (with patents filed for the assignee):

Benoit De Lescure (34 out of 34 patents)

Moez Cherif (17 out of 17 patents)

John D Coddington (12 out of 26 patents)

4. Parimal Gaikwad (9 out of 12 patents)

5. Xavier Van Ruymbeke (9 out of 11 patents)

6. Craig Stephen Forrest (8 out of 19 patents)

7. Philippe Boucard (8 out of 32 patents)

8. David Alan Kruckemyer (8 out of 13 patents)

9. Syed Ijlal Ali Shah (7 out of 7 patents)

10. Alexis Boutiller (6 out of 6 patents)

11. Monica Tang (6 out of 6 patents)

12. Mohammed Khaleeluddin (6 out of 6 patents)

13. Khaled Labib (5 out of 5 patents)

14. Jonah Probell (5 out of 20 patents)

15. Michael G Frank (5 out of 69 patents)

Core Competencies:

Network-On-Chip

Topology Synthesis

Cache Coherence

Fault Detection

Performance Prediction

Virtual Channels

Transaction Management

Pipeline Stages

Incremental Synthesis

Interconnect Design

Data Latency

Quality Metrics

103 patents: Sort by Forward Citations

1. 12724708 - Writing data and resilience bits to register memory (2026-09-01),

2. 12717708 - Modulo operations for interleaved memory having non-power-of-two channels (2026-08-25),

3. 12711070 - HARDWARE PIPELINE FOR CACHE COHERENT INTERCONNECT INCLUDING SNOOP FILTERS (2026-08-18),

4. 12694192 - Use of AI image generation model to create high-level visualization of a network-on-chip (2026-07-28),

5. 12670097 - System and method for managing event messages in a cache coherent interconnect (2026-06-30),

6. 12657155 - System and method for generation of networks-on-chip (NoCs) (2026-06-16),

7. 12645595 - Point-of-coherence exclusive monitor for a cache coherent interconnect for a multi-core electronic system (2026-06-02),

8. 12524590 - Synthesis of a network-on-chip (NoC) for insertion of pipeline stages (2026-01-13),

9. 12517829 - Processing writes to multiple targets in a directory-based cache coherent electronic system (2026-01-06),

10. 12511466 - System and method for generation of a report and debug of address transformations in electronic systems described with IP-XACT standard (2025-12-30),

11. 12450036 - System and method for scripting generators (2025-10-21),

12. 12438829 - System and method for deadlock detection in network-on-chip (NoC) having external dependencies (2025-10-07),

13. 12411801 - System and method for transaction broadcast in a network on chip (2025-09-09),

14. 12380055 - System and method for performing transaction aggregation in a network-on-chip (NoC) (2025-08-05),

15. 12348382 - Incremental topology modification of a network-on-chip (2025-07-01),

Arteris, Inc. is a global leader in interconnect IP and AI-centric SoC designs. The company provides SoC fabric technology and interconnect IP solutions to the world's leading semiconductor and automotive companies. Arteris offers innovative and patented technologies for efficient, high-performance, and low-power on-chip communications. With a focus on artificial intelligence and advanced driving assistance systems (ADAS), Arteris enables the smart and connected future.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Sep 22 2026

103 Patents

#6 in Campbell, CA

#840 in California

#3,684 in US

#7,571 in the World

Campbell, CA, United States of America

Arteris, Inc.

Forward Citations = 207

62 inventors:

Benoit De Lescure (34 out of 34 patents)

Moez Cherif (17 out of 17 patents)

John D Coddington (12 out of 26 patents)

4. Parimal Gaikwad (9 out of 12 patents)

5. Xavier Van Ruymbeke (9 out of 11 patents)

Please report any incorrect information to [email protected]

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