Austin, TX, United States of America

John D Coddington

This inventor holds 26 USPTO granted patents and 2 published patent applications and 1 EPO patent, primarily in Network-On-Chip Design. Top assignees: Arteris, Inc., Motorola Corporation, Tandem Computers Incorporated. Active years: 1995-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John D Coddington. Retrieved from https://idiyas.com/inventor/john-d-coddington

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 96.2

 

Average Co-Inventor Count = 1.9

ph-index = 8

Forward Citations = 465(Granted Patents)


Location History:

  • Austin, TX (US) (1995 - 1997)
  • Cedar Park, TX (US) (1997 - 2024)

Company Filing History:


Years Active: 1995-2025

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Areas of Expertise:
Transaction Broadcast
Interface Protection
Buffered Switch
Virtual Channels
Data Latency Management
Adaptive Resource Management
High Voltage Input Buffer
Error Detection
Fault-Tolerant Systems
Cache Replacement
Multiprocessor System
Data Communication
26 patents (USPTO):Explore Patents

Title: Innovations of John D. Coddington: Pioneering Advances in Network-On-Chip Technology

Introduction

John D. Coddington, based in Austin, TX, is a prolific inventor with an impressive portfolio of 23 patents. His work has significantly contributed to the fields of electronic design and network architecture, showcasing his expertise and innovative thinking in technology.

Latest Patents

Coddington's latest innovations include two notable patents that reflect his cutting-edge approach to technology. The first, titled "Broadcast Adapters in a Network-On-Chip," describes a broadcast adapter used for transmitting transactions in the form of packets from an initiator to multiple targets. This system allows multiple responses from the targets to be combined and sent back to the initiator, optimizing communication efficiency within network-on-chip designs.

His second patent, "System and Method for Using Interface Protection Parameters," introduces a framework for integrating interface protection into electronic designs. This system employs defined parameters to develop an interface protection model, enhancing security and functionality in hardware implementations. The model facilitates automatic generation of hardware descriptions based on electronic design and protection parameters, demonstrating Coddington's innovative problem-solving capabilities.

Career Highlights

Throughout his career, Coddington has been associated with prominent companies, including Motorola Corporation and Arteris, Inc. His work in these organizations has helped advance technologies that affect a wide range of applications, particularly in semiconductor and network design fields.

Collaborations

Coddington has collaborated with other notable professionals in the industry, including Benoit de Lescure and Syed Ijlal Ali Shah. These partnerships reflect his commitment to teamwork and sharing knowledge, which often leads to groundbreaking innovations and advancements in technology.

Conclusion

John D. Coddington stands as a testament to the spirit of innovation in technology. His patents and career achievements not only underscore his role as a pioneer in network-on-chip systems but also highlight the vital contributions made by inventors in the ever-evolving landscape of electronic design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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