Arteris, Inc.

Motorola Corporation

Tandem Computers Incorporated

Oracle International Corporation

Nxp Usa, Inc.

John D Coddington

Benoit De Lescure

Syed Ijlal Ali Shah

David J Garcia

William P Bunton

William J Watson

David P Sonnier

Susan S Meredith

Xavier Van Ruymbeke

Sylvain Meliciani

Frederic Greus

John C Krause

William Edward Baker

Geoffrey I Iswandhi

Daniel L Fowler

Frank A Williams

Linda Ellen Zalzala

Paul N Hintikka

Chau-Shing Hui

Boon Chuan

Sanjay Despande

Perry H Pelley

Robert W Horst

Sanjay Raghunath Deshpande

John Michael Brown

William F Bruckert

Douglas E Jewett

Richard W Cutts, Jr

Thang Q Nguyen

Steven C Meyers

Stephen G Low

Patricia L Whiteside

Randall G Banton

James Stevens Klecka

Gary F Campbell

Curtis Willard Jones, Jr

Stephen H Miller

Barry Lee Drexler

Harry Frank Elrod

Perry H Pelley Iii

A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.

System and method for transaction broadcast in a network on chip

A system and method for generation of a hardware description for adding interface protection scheme to an electronic design. The electronic design and interface protection scheme are defined as parameters. An interface protection model includes interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description module uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding.

System and method for using interface protection parameters

A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.

Network-on-chip (NoC) with a broadcast switch system

Broadcast adapters in a network-on-chip

A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.

Switch with virtual channels for soft locking in a network-on-chip (NoC)

A buffered switch system for end-to-end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.

System and method for data loss and data latency management in a network-on-chip with buffered switches

A buffered switch system, data loss and latency management system, and methods of use are presented. The disclosure provides, generally, a buffered switch system for end to end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.

Management of a buffered switch having virtual channels for data transmission within a network

Broadcast switch system in a network-on-chip (NoC)

Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.

A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.

System and method for using soft lock with virtual channels in a network-on-chip (NoC)

System and method for interface protection

A resource arbiter in a system with multiple shared resources and multiple requestors may implement an adaptive resource management approach that takes advantage of time-varying requirements for granting access to at least some of the shared resources. For example, due to pipelining, signal timing issues, or a lack of information, more resources than are required to perform a task may need to be available for allocation to a requestor before its request for the needed resources is granted. The requestor may request only the resources it needs, relying on the arbiter to determine whether additional resources are required in order to grant the request. The arbiter may park a high priority requestor on idle resources, thus allowing requests for those resources by the high priority requestor to be granted on the first clock cycle of a request. Other requests may not be granted until at least a second clock cycle.

Adaptive resource management in a pipelined arbiter

A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way in a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed.

Least recently used (LRU) cache replacement implementation using a FIFO storing indications of whether a way of the cache was most recently accessed

A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit ( ) and a level shifter ( ). The input buffer ( ) will receive an input signal via a chip pad ( ). The input signal from trip pad ( ) will be provided to an inverter stack ( ) that contains or is coupled to protection transistors ( and ). The protection transistors are biased by a reference generator ( ) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad ( ). By using the circuit ( ), the trigger point of the inverter stack ( ) can be dynamically adjusted for any OVDD ( ) value whereby input buffer performance is improved and made more flexible.

High voltage input buffer made by a low voltage process and having a self-adjusting trigger point

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Austin, TX, United States of America

John D Coddington