The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Sep. 06, 2022
Applicant:
Arteris, Inc., Campbell, CA (US);
Inventors:
Mokhtar Hirech, Sunnyvale, CA (US);
Benoit De Lescure, Campbell, CA (US);
Assignee:
ARTERIS, INC., Campbell, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/3323 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/3323 (2020.01);
Abstract
A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.
Hirech, Mokhtar. (2026). System and method for area and timing assessment of a network-on-chip (noc) implementation (U.S. Patent No. 12769910). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12769910
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile