The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jul. 01, 2022
Applicant:

Arteris, Inc., Campbell, CA (US);

Inventors:

Benoit Lafage, Les Lilas, FR;

Insaf Meliane, Asnières-sur-seine, FR;

Nabil Guissouma, Paris, FR;

Assignee:

ARTERIS, INC., Campbell, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 11/32 (2006.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 11/321 (2013.01); G06F 30/394 (2020.01);
Abstract

In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that create a system-level address map and create a report. A system description of an electronic system (e.g., integrated circuit (IC)) is received that includes configuration parameters. A tree representation of the system is created based on the interconnect of the system. Each port of the system is assigned a tree node. To create a corresponding system-level address map, the tree representation is traversed from target(s) to initiator(s), calculating the address transformation at each node. A report of the system-level address map is created, and defects such as address duplication, missing addresses, etc. can be identified and reported to the user.


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