For the Inventor, By the Inventor

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Santa Clara, CA, United States of America

Ampere Computing LLC

USPTO Granted Patents = 83

EPO Patents = 12

Trademarks = 11

Forward Citations = 106

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108 inventors (with patents filed for the assignee):

Benjamin C Chaffin (10 out of 24 patents)

Alfred Yeung (9 out of 15 patents)

Nagi Aboulenein (9 out of 23 patents)

4. Sandeep Brahmadathan (9 out of 9 patents)

5. Jonathan Christopher Perry (8 out of 12 patents)

6. Bret Leslie Toll (8 out of 8 patents)

7. Matthew Robert Erler (8 out of 9 patents)

8. Harb Abdulhamid (8 out of 11 patents)

9. Stephan Jourdan (7 out of 94 patents)

10. Richard James Shannon (7 out of 7 patents)

11. Keyur Chudgar (6 out of 19 patents)

12. Massimo Sutera (6 out of 14 patents)

13. Jared Eric Bendt (6 out of 6 patents)

14. Robert J Safranek (5 out of 55 patents)

15. Kjeld Svendsen (5 out of 14 patents)

Core Competencies:

Cache Coherency

Memory Resource Control

Boot Security

Error Correction Code

Multi-Level Caching

Instruction Scheduling

Processor-Based Systems

Memory Utilization

On-Die Voltage Detection

System-on-Chip

Data Management

Network Nodes

83 patents: Sort by Forward Citations

1. 12754847 - System and method for handling cache updates (2026-10-06),

2. 12748705 - Multi-core processor-based system implementing directed page table entry invalidation (2026-09-29),

3. 12717583 - Processor macro-operation fusion (2026-08-25),

4. 12699568 - Runtime adaptive prefetching in a many-core system (2026-08-04),

5. 12681865 - Processors with toggleable memory tagging extensions and related methods (2026-07-14),

6. 12664094 - Memory coherence with early store completion (2026-06-23),

7. 12645800 - Method and system for patching a boot process (2026-06-02),

8. 12645628 - Method and system for data transactions on a communications interface (2026-06-02),

9. 12639069 - Providing additional operations for a functional unit of a processor core (2026-05-26),

10. 12613803 - Cache memory system employing a multiple-level hierarchy cache coherency architecture (2026-04-28),

11. 12554640 - Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system (2026-02-17),

12. 12549479 - Apparatus and method of routing a request in a mesh network (2026-02-10),

13. 12493552 - Performing snoop filter replacement based on history-augmented victimization priority values of snoop filter entries in processor-based devices (2025-12-09),

14. 12474848 - Techniques for memory resource control using memory resource partitioning and monitoring (2025-11-18),

15. 12451206 - Extending functionality of memory controllers using a loopback mode for testing in a processor-based device (2025-10-21),

Company Overview

Ampere Computing LLC, based in Santa Clara, CA, specializes in advanced cache memory systems, focusing on enhancing performance and efficiency in processor-based systems. The company is at the forefront of developing technologies related to cache coherency, memory resource control, and multi-level caching, which are critical for optimizing memory utilization in modern computing environments. Additionally, Ampere emphasizes boot security and error correction code to ensure reliable and secure operations in its innovative solutions.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

83 Patents

#45 in Santa Clara, CA

#1,036 in California

#4,473 in US

#9,158 in the World

Santa Clara, CA, United States of America

Ampere Computing LLC

Forward Citations = 106

108 inventors:

Benjamin C Chaffin (10 out of 24 patents)

Alfred Yeung (9 out of 15 patents)

Nagi Aboulenein (9 out of 23 patents)

4. Sandeep Brahmadathan (9 out of 9 patents)

5. Jonathan Christopher Perry (8 out of 12 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Ampere Computing LLC. Retrieved from https://idiyas.com/company/ampere-computing

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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