Cache memory system employing a multiple-level hierarchy cache coherency architecture

Abstract

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions