The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Jun. 16, 2021
Applicant:

Ampere Computing Llc, Santa Clara, CA (US);

Inventors:

Matthew Robert Erler, Portland, OR (US);

Robert James Safranek, Portland, OR (US);

Robert Joseph Toepfer, Portland, OR (US);

Sandeep Brahmadathan, Dublin, CA (US);

Shailendra Ramrao Chavan, Brentwood, CA (US);

Jonglih Yu, Sunnyvale, CA (US);

Assignee:

Ampere Computing LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01); G06F 11/10 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 11/1004 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0038 (2013.01);
Abstract

A system-on-a-chip (SoC) with one or more processors and other system components may have one or more peripheral component interconnect express (PCIe) physical connections between the processors and other system components to provide agent-to-agent communication. The agents on the communication fabric of the SoC may transmit data through the hardware PCIe interface where a transmitter device of an agent or digital logic component receives at least one data block for transmission and receives a flag corresponding to the at least one data block. The transmitter device may then send, via a PCIe physical layer, the received data blocks as a payload of a packet based on the flag, where the packet has a PCIe compliant header. The payload of the packet with the PCIe header may be entirely composed of these data blocks or flits from the agent.


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