The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Mar. 15, 2024
Applicant:

Ampere Computing Llc, Santa Clara, CA (US);

Inventors:

Ramya Jayaram Masti, Hillsboro, OR (US);

Benjamin Crawford Chaffin, Portland, OR (US);

Vincent Edward Von Bokern, Rescue, CA (US);

Raymond S. Tetrick, Portland, OR (US);

Assignee:

Ampere Computing LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 9/455 (2018.01); G06F 12/1036 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 9/45558 (2013.01); G06F 12/1036 (2013.01); G06F 2009/45583 (2013.01);
Abstract

A first core in a processor-based system may obtain information that identifies cores in a first set of cores, where the information also indicates that at least one core of the first set of cores is assigned to execute instructions for a first VM. The first core sends a first message directed to the first set of cores to invalidate copies of a first page table entry of the first VM in the core TLBs of the first set of cores. A message to invalidate copies of a page table entry may be sent in advance of modifying the page table entry of the first VM in a memory system. Sending a message directed to the first set of cores to invalidate copies of page table entries in the first set of cores, instead of an invalidation message broadcast to all cores in the processor-based system, reduces communication traffic.


Find Patent Forward Citations

Loading…