Multi-core processors evicting cache lines from lower-level caches to higher-level caches by core-to-core transfers

Abstract

To reduce a number of cache line transfers in a multi-core processor that includes a cache manager circuit to manage coherence of a cache memory system, a source central processing unit (CPU) core that is evicting a cache line from an associated lower-level cache memory transfers the evicted cache line to another core for storage in a 'slice' of a higher-level cache memory associated with the other core, rather than to the cache manager circuit. In some examples, the cache manager circuit receives a request for the eviction, determines which CPU core will store the target CPU core for the evicted cache line, and notifies the source CPU core of the identification of the target CPU core. In some examples, the cache manager circuit informs the target CPU core that the evicted cache line will be transferred.