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San Jose, CA, United States of America

Alliance Semiconductor Corporation

USPTO Granted Patents = 84

% Expired Patents = 9.5

Forward Citations = 1,464

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32 inventors (with patents filed for the assignee):

Chitranjan N Reddy (39 out of 46 patents)

Ritu Shrivastava (19 out of 25 patents)

Subramani Kengeri (10 out of 45 patents)

4. Ajit K Medhekar (10 out of 13 patents)

5. Spencer H Greene (8 out of 33 patents)

6. Kenneth A Poteet (7 out of 7 patents)

7. Perumal Ratnam (6 out of 23 patents)

8. Andrew D Daniel (6 out of 6 patents)

9. Michael C Stephens, Jr (5 out of 20 patents)

10. Vipul C Patel (5 out of 6 patents)

11. Abhijit Ray (4 out of 9 patents)

12. Chaitanya Palusa (3 out of 5 patents)

13. Damodar Reddy Thummalapally (3 out of 28 patents)

14. Thomas Alexander (3 out of 3 patents)

15. Mohit Sharma (2 out of 7 patents)

Core Competencies:

DRAM Cells

Flash EPROM

Memory Architecture

Low Latency

Synchronization

High Performance

Synchronous RAM

Voltage Translation

Shared Memory

Integrated Circuits

Storage Capacitor

Dynamic Memory

84 patents: Sort by Forward Citations

1. 7027548 - Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings (2006-04-11),

2. 6921688 - Method of and apparatus for integrating flash EPROM and SRAM cells on a common substrate (2005-07-26),

3. 6903434 - Method and apparatus for integrating flash EPROM and SRAM cells on a common substrate (2005-06-07),

4. 6839799 - Method for the prioritization of database entries (2005-01-04),

5. 6766317 - Range check cell and a method for the use thereof (2004-07-20),

6. 6738917 - Low latency synchronization of asynchronous data (2004-05-18),

7. 6687256 - Recoverable cut-through buffer and method (2004-02-03),

8. 6646463 - Impedance emulator (2003-11-11),

9. 6589834 - Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current (2003-07-08),

10. 6476666 - Bootstrapped charge pump (2002-11-05),

11. 6472267 - DRAM cell having storage capacitor contact self-aligned to bit lines and word lines (2002-10-29),

12. 6459647 - Split-bank architecture for high performance SDRAMs (2002-10-01),

13. 6456537 - Techniques for erasing an erasable programmable read only memory (EPROM) cell (2002-09-24),

14. 6442098 - High performance multi-bank compact synchronous DRAM architecture (2002-08-27),

15. 6429076 - Flash EPROM memory cell having increased capacitive coupling and method of manufacture thereof (2002-08-06),

Company Overview

Alliance Semiconductor Corporation, based in San Jose, California, specializes in advanced memory architecture solutions. The company focuses on the development and manufacturing of high-performance memory technologies, including DRAM cells and Flash EPROM. Their expertise extends to low latency and synchronization techniques, ensuring efficient data processing and storage. With a commitment to innovation, Alliance Semiconductor plays a pivotal role in enhancing memory performance across various applications, catering to the evolving needs of the technology landscape.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

84 Patents

#127 in San Jose, CA

#1,023 in California

#4,431 in US

#9,067 in the World

San Jose, CA, United States of America

Alliance Semiconductor Corporation

Forward Citations = 1,464

32 inventors:

Chitranjan N Reddy (39 out of 46 patents)

Ritu Shrivastava (19 out of 25 patents)

Subramani Kengeri (10 out of 45 patents)

4. Ajit K Medhekar (10 out of 13 patents)

5. Spencer H Greene (8 out of 33 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Alliance Semiconductor Corporation. Retrieved from https://idiyas.com/company/alliance-semiconductor

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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