The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2002
Filed:
May. 29, 2001
Applicant:
Inventor:
Perumal Ratnam, Fremont, CA (US);
Assignee:
Alliance Semiconductor, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/604 ; G11C 1/606 ;
U.S. Cl.
CPC ...
G11C 1/604 ; G11C 1/606 ;
Abstract
Techniques for improved erasing of an EPROM are described. As a method, a a drain potential of a first polarity is applied to the drain node of a selected memory cell having a first polarity concurrently with applying a gate potential of a second polarity to the gate of the selected memory cell having a second polarity. The drain and the gate polarities are then maintained until the charge has been removed from the floating gate structure of the selected memory cell as determined by a verification protocol.
Ratnam, Perumal. (2002). Techniques for erasing an erasable programmable read only memory (eprom) cell (U.S. Patent No. 6456537). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6456537
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile