The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Feb. 06, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chin-Chieh Yang, New Taipei, TW;

Chih-Yang Chang, Yuanlin Township, TW;

Chang-Sheng Liao, Zhudong Township, TW;

Hsia-Wei Chen, Taipei, TW;

Jen-Sheng Yang, Keelung, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Sheng-Hung Shih, Hsinchu, TW;

Wen-Ting Chu, Kaohsiung, TW;

Manish Kumar Singh, Hsin-Chu, TW;

Chi-Tsai Chen, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 11/1653 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.


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