The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2018
Filed:
May. 08, 2015
Intel Corporation, Santa Clara, CA (US);
Benjamin Chu-Kung, Hillsboro, OR (US);
Van Le, Beaverton, OR (US);
Robert Chau, Portland, OR (US);
Sansaptak Dasgupta, Hillsboro, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Niti Goel, Austin, TX (US);
Jack Kavalieros, Portland, OR (US);
Matthew Metz, Portland, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Han Wui Then, Portland, OR (US);
Nancy Zelick, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a 'all-around gate' structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.