The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2017
Filed:
Feb. 15, 2016
Applied Materials, Inc., Santa Clara, CA (US);
Wei V. Tang, Santa Clara, CA (US);
Paul F. Ma, Santa Clara, CA (US);
Steven C. H. Hung, Sunnyvale, CA (US);
Michael Chudzik, Mountain View, CA (US);
Siddarth Krishnan, Newark, CA (US);
Wenyu Zhang, Sunnyvale, CA (US);
Seshadri Ganguli, Sunnyvale, CA (US);
Naomi Yoshida, Sunnyvale, CA (US);
Lin Dong, San Jose, CA (US);
Yixiong Yang, San Jose, CA (US);
Liqi Wu, Santa Clara, CA (US);
Shih Chung Chen, Cupertino, CA (US);
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Abstract
Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.