The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Feb. 01, 2016
Stats Chippac, Ltd., Singapore, SG;
KyungMoon Kim, Gyeonggi-do, KR;
KooHong Lee, Seoul, KR;
JaeHak Yee, Seoul, KR;
YoungChul Kim, Kyoungki-do, KR;
Lan Hoang, San Jose, CA (US);
Pandi C. Marimuthu, Singapore, SG;
Steve Anderson, San Ramon, CA (US);
HunTeak Lee, Gyeonggi-do, KR;
HeeJo Chi, Kyoungki-do, KR;
STATS ChipPAC Pte. Ltd., Singapore, SG;
Abstract
A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.