The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Apr. 26, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ju-Shi Chen, Tainan, TW;

Cheng-Ying Ho, Minxiong Township, TW;

Chun-Chieh Chuang, Tainan, TW;

Sheng-Chau Chen, Tainan, TW;

Shih Pei Chou, Tainan, TW;

Hui-Wen Shen, Kaohsiung, TW;

Dun-Nian Yaung, Taipei, TW;

Ching-Chun Wang, Tainan, TW;

Feng-Chi Hung, Chu-Bei, TW;

Shyh-Fann Ting, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1082 (2013.01);
Abstract

Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 Å. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may also be employed to promote topographic uniformity at wafer edges. Improved planarity of wafers presented for hybrid bonding results in improved bond uniformity for 3DIC devices formed thereby.


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