The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2016
Filed:
Mar. 08, 2013
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Gerben Doornbos, Leuven, BE;
Mark van Dal, Heverlee, BE;
Georgios Vellianitis, Heverlee, BE;
Blandine Duriez, Brussels, BE;
Krishna Kumar Bhuwalka, Leuven, BE;
Richard Kenneth Oxland, Brussels, BE;
Martin Christopher Holland, Leuven, BE;
Yee-Chaung See, Hsin-Chu, TW;
Matthias Passlack, Huldenberg, BE;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.