Yee-Chaung See

Title: Innovations of Yee-Chaung See

Introduction

Yee-Chaung See is a prominent inventor based in Hsin-Chu, Taiwan. She has made significant contributions to the field of semiconductor technology, holding 2 patents that showcase her innovative approach to device manufacturing.

Latest Patents

Her latest patents include a FinFET with a channel backside passivation layer device and method. This invention involves a FinFET structure that comprises a template layer on a substrate, a buffer layer above the template, and a channel backside passivation layer over the buffer. Additionally, a gate insulator layer is in contact with both the channel layer and the channel backside passivation layer. The design allows for enhanced performance by potentially incorporating aluminum in the buffer layer and a III-V semiconductor compound in the channel layer. Another notable patent is a manufacturing method for semiconductor devices aimed at mitigating short channel effects. This method involves forming gate structures on a substrate and strategically implanting dopants to create halo regions, optimizing the performance of MOS transistors.

Career Highlights

Yee-Chaung See is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. Her work focuses on advancing semiconductor technologies and improving device performance through innovative designs and manufacturing techniques.

Collaborations

Throughout her career, she has collaborated with notable colleagues, including Gerben Doornbos and Mark Van Dal. These partnerships have contributed to her success and the advancement of semiconductor technology.

Conclusion

Yee-Chaung See's contributions to the semiconductor field through her patents and work at Taiwan Semiconductor Manufacturing Company Limited highlight her role as an influential inventor. Her innovative approaches continue to shape the future of semiconductor technology.