The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7449386 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 11, 2008

Filed:

Nov. 16, 2006
Applicants:

Chung-te Lin, Tainan, TW;

Di-houng Lee, Austin, TX (US);

Yee-chaung See, Dallas, TX (US);

Inventors:

Chung-Te Lin, Tainan, TW;

Di-Houng Lee, Austin, TX (US);

Yee-Chaung See, Dallas, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a plurality of MOS transistors includes forming gate structures in first and second regions on a substrate and forming mask portions only between adjacent drain sides of the respective gate structures only in the first region. Dopant of a first conductivity type that is the same as that of the substrate, is implanted at first and second angles in both the first and second regions to form halo regions only in source sides under the gate structures in the first region and in both source and drain sides under the gate structures in the second region.


Find Patent Forward Citations

Lin, Chung-Te. (2008). Manufacturing method for semiconductor device to mitigate short channel effects (U.S. Patent No. 7449386). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7449386

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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