The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Jun. 10, 2011
Teck-gyu Kang, San Jose, CA (US);
Wei-shun Wang, Palo Alto, CA (US);
Hiroaki Sato, Yokohama, JP;
Kiyoaki Hashimoto, Yokohama, JP;
Yoshikuni Nakadaira, Hodogaya-Ku, JP;
Norihito Masuda, Yokohama, JP;
Belgacem Haba, Saratoga, CA (US);
Ilyas Mohammed, Santa Clara, CA (US);
Philip Damberg, Cupertino, CA (US);
Teck-Gyu Kang, San Jose, CA (US);
Wei-Shun Wang, Palo Alto, CA (US);
Hiroaki Sato, Yokohama, JP;
Kiyoaki Hashimoto, Yokohama, JP;
Yoshikuni Nakadaira, Hodogaya-Ku, JP;
Norihito Masuda, Yokohama, JP;
Belgacem Haba, Saratoga, CA (US);
Ilyas Mohammed, Santa Clara, CA (US);
Philip Damberg, Cupertino, CA (US);
Tessera, Inc., San Jose, CA (US);
Abstract
A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.