The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
May. 28, 2010
Takeshi Senda, Niigata, JP;
Hiromichi Isogai, Niigata, JP;
Eiji Toyoda, Niigata, JP;
Koji Araki, Niigata, JP;
Tatsuhiko Aoki, Niigata, JP;
Haruo Sudo, Niigata, JP;
Koji Izunome, Niigata, JP;
Susumu Maeda, Hadano, JP;
Kazuhiko Kashima, Hadano, JP;
Hiroyuki Saito, Niigata, JP;
Takeshi Senda, Niigata, JP;
Hiromichi Isogai, Niigata, JP;
Eiji Toyoda, Niigata, JP;
Koji Araki, Niigata, JP;
Tatsuhiko Aoki, Niigata, JP;
Haruo Sudo, Niigata, JP;
Koji Izunome, Niigata, JP;
Susumu Maeda, Hadano, JP;
Kazuhiko Kashima, Hadano, JP;
Hiroyuki Saito, Niigata, JP;
Global Wafers Japan Co., Ltd., Niigata, JP;
Abstract
A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface regionwhich is a defect-free region and a bulk regionincluding void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.