The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2015
Filed:
Apr. 12, 2012
Jeremiah Hebding, Poughkeepsie, NY (US);
Megha Rao, Clifton Park, NY (US);
Colin Mcdonough, Albany, NY (US);
Matthew Smalley, Ballston Lake, NY (US);
Douglas Duane Coolbaugh, Highland, NY (US);
Joseph Piccirillo, Jr., Clifton Park, NY (US);
Stephen G. Bennett, Niskayuna, NY (US);
Michael Liehr, Guilderland, NY (US);
Daniel Pascual, Wolcott, VT (US);
Jeremiah Hebding, Poughkeepsie, NY (US);
Megha Rao, Clifton Park, NY (US);
Colin McDonough, Albany, NY (US);
Matthew Smalley, Ballston Lake, NY (US);
Douglas Duane Coolbaugh, Highland, NY (US);
Joseph Piccirillo, Jr., Clifton Park, NY (US);
Stephen G. Bennett, Niskayuna, NY (US);
Michael Liehr, Guilderland, NY (US);
Daniel Pascual, Wolcott, VT (US);
The Research Foundation of State University of New York, Albany, NY (US);
Abstract
An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.