The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Jul. 23, 2014
Applicant:

Xintec Inc., Jhongli, Taoyuan County, TW;

Inventors:

Yen-Shih Ho, Kaohsiung, TW;

Tsang-Yu Liu, Zhubei, TW;

Shu-Ming Chang, New Taipei, TW;

Yu-Lung Huang, Daxi Township, TW;

Chao-Yen Lin, New Taipei, TW;

Wei-Luen Suen, New Taipei, TW;

Chien-Hui Chen, Zhongli, TW;

Assignee:

Xintec, Inc., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/48 (2006.01); H01L 21/44 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/49 (2013.01); H01L 24/43 (2013.01); H01L 23/3121 (2013.01); H01L 24/85 (2013.01); H01L 2924/14 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/146 (2013.01); H01L 2224/48599 (2013.01);
Abstract

A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.


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