The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2014
Filed:
Sep. 27, 2012
Marko Radosavljevic, Beaverton, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Benjamin Chu-kung, Hillsboro, OR (US);
Dipanjan Basu, Hillsboro, OR (US);
Sanaz K. Gardner, Portland, OR (US);
Satyarth Suri, Hillsboro, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Han Wui Then, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Benjamin Chu-Kung, Hillsboro, OR (US);
Dipanjan Basu, Hillsboro, OR (US);
Sanaz K. Gardner, Portland, OR (US);
Satyarth Suri, Hillsboro, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Han Wui Then, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.