The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 2010
Filed:
Feb. 14, 2008
Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode
Justin K. Brask, Portland, OR (US);
Jack Kavalieros, Portland, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Uday Shah, Portland, OR (US);
Chris E. Barns, Portland, OR (US);
Matthew V. Metz, Hillsboro, OR (US);
Suman Datta, Beaverton, OR (US);
Annalisa Cappellani, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Justin K. Brask, Portland, OR (US);
Jack Kavalieros, Portland, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Uday Shah, Portland, OR (US);
Chris E. Barns, Portland, OR (US);
Matthew V. Metz, Hillsboro, OR (US);
Suman Datta, Beaverton, OR (US);
Annalisa Cappellani, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.