The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2010
Filed:
Sep. 03, 2004
Akira Koshiishi, Nirasaki, JP;
Hideaki Tanaka, Nirasaki, JP;
Nobuyuki Okayama, Nirasaki, JP;
Masaaki Miyagawa, Nirasaki, JP;
Shunsuke Mizukami, Nirasaki, JP;
Wataru Shimizu, Nirasaki, JP;
Jun Hirose, Nirasaki, JP;
Toshikatsu Wakaki, Nirasaki, JP;
Tomonori Miwa, Nirasaki, JP;
Jun Ooyabu, Nirasaki, JP;
Daisuke Hayashi, Nirasaki, JP;
Akira Koshiishi, Nirasaki, JP;
Hideaki Tanaka, Nirasaki, JP;
Nobuyuki Okayama, Nirasaki, JP;
Masaaki Miyagawa, Nirasaki, JP;
Shunsuke Mizukami, Nirasaki, JP;
Wataru Shimizu, Nirasaki, JP;
Jun Hirose, Nirasaki, JP;
Toshikatsu Wakaki, Nirasaki, JP;
Tomonori Miwa, Nirasaki, JP;
Jun Ooyabu, Nirasaki, JP;
Daisuke Hayashi, Nirasaki, JP;
Tokyo Electron Limited, Tokyo, JP;
Abstract
A focus ring and a plasma processing apparatus capable of improving an in-surface uniformity of a surface and reducing occurrences of deposition on a backside surface of a peripheral portion of a semiconductor wafer compared to a conventional case are provided. Installed in a vacuum chamber is a susceptor for mounting the semiconductor wafer thereon and a focus ring is installed to surround the semiconductor wafer mounted on the susceptor. The focus ring includes an annular lower member made of a dielectric, and an annular upper member made of a conductive material and mounted on the lower member. The upper member includes a flat portion which is an outer peripheral portion having a top surface positioned higher than a surface to be processed of the semiconductor wafer W, and an inclined portion which is an inner peripheral portion inclined inwardly.