The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2009
Filed:
May. 24, 2006
Hamza Yilmaz, Saratoga, CA (US);
Daniel Calafut, San Jose, CA (US);
Christopher Boguslaw Kocon, Mountaintop, PA (US);
Steven P. Sapp, Santa Cruz, CA (US);
Dean E. Probst, West Jordan, UT (US);
Nathan L. Kraft, Pottsville, PA (US);
Thomas E. Grebs, Mountaintop, PA (US);
Rodney S. Ridley, Scarborough, ME (US);
Gary M. Dolny, Mountaintop, PA (US);
Bruce D. Marchant, Murray, UT (US);
Joseph A. Yedinak, Mountaintop, PA (US);
Hamza Yilmaz, Saratoga, CA (US);
Daniel Calafut, San Jose, CA (US);
Christopher Boguslaw Kocon, Mountaintop, PA (US);
Steven P. Sapp, Santa Cruz, CA (US);
Dean E. Probst, West Jordan, UT (US);
Nathan L. Kraft, Pottsville, PA (US);
Thomas E. Grebs, Mountaintop, PA (US);
Rodney S. Ridley, Scarborough, ME (US);
Gary M. Dolny, Mountaintop, PA (US);
Bruce D. Marchant, Murray, UT (US);
Joseph A. Yedinak, Mountaintop, PA (US);
Fairchild Semiconductor Corporation, South Portland, MA (US);
Abstract
A method for forming a shielded gate field effect transistor includes the following steps. Trenches extending into a silicon region are formed using a mask that includes a protective layer. A shield dielectric layer lining sidewalls and bottom of each trench is formed. A shield electrode is formed in a bottom portion of each trench. Protective spacers are formed along upper sidewalls of each trench. An inter-electrode dielectric is formed over the shield electrode. The protective spacers and the protective layer of the mask prevent formation of inter-electrode dielectric along the upper sidewalls of each trench and over mesa surfaces adjacent each trench. A gate electrode is formed in each trench over the inter-electrode dielectric.